The design of complex computer hardware no longer begins with a circuit diagram. Instead, it begins with a software program that describes the behavior or functionality of a circuit. This software program is written in a hardware description language (HDL) that defines an algorithm to be performed with limited implementation details. Designers direct behavioral synthesis tools to generate alternate architectures by modifying constraints (such as clock period, number and type of data path elements, and desired number of clock cycles). Behavioral synthesis tools convert the HDL program into a register transfer level (RTL) description. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit. One characteristic of RTL code is that the RTL code is specified for each clock event, while a behavioral specification has a more abstract timing or no timing at all. Going from a behavioral specification to RTL code (manually or automatically) requires a determination of the clocked behavior. In behavioral synthesis this essential step is called scheduling.
An example HDL source code is shown in Table 1 below that declares three variables, a, b, and c, that are arrays. Each array contains 1024, 8-bit words. The code first declares a “subtype” to define the type of each element in the array. The code then defines a “type” to represent the array itself. Finally, the variables are declared, each variable representing an array.
TABLE 1SUBTYPE word IS unsigned (7 DOWNTO 0);TYPE array_type IS ARRAY (integer RANGE <>) of word,VARIABLE a, b, c: array_type (0 to 1023)
Generally, the variables are accessed using loops, such as the loop shown below in Table 2.
TABLE 2FOR i IN 0 TO 15 LOOP a(i) := b (i) * c(i) +4;END LOOP;
After the designer completes the HDL source code (which may include pragma statements or other directives), the designer runs the source code through the synthesis tool. The synthesis tool generates a report that the designer can use to analyze the performance of the circuit. For example, the user can examine the area and latency of the circuit to determine whether the current loop configuration is acceptable. If the loop configuration is not acceptable, the designer must return to an editor, re-edit the source code to unroll or pipeline loops, and run the source code through the synthesis tool again. Such a technique for modifying the design is time consuming and inefficient. Moreover, the designer cannot easily visualize how the loop configuration changes the design while modifying the source code.
It is desirable, therefore, to provide a synthesis tool that allows a designer to easily identify loops where execution time is relatively inefficient, and unroll or pipeline those loops more quickly and simply. Scheduling determines the number of cycles to perform a static segment of the specification (e.g., one iteration of a loop). How this translates into the dynamic timing of the design depends if and how often each code segment is executed. Segments of the code are repeated over and over again in loops, so the user needs a way to go from the static timing of a scheduled specification to the dynamic timing when executing the specification with actual input values. It is desirable to allow a designer to readily visualize relative loop execution time in the context of dynamic timing.